1. Field of the Invention
The present invention relates to a solid-state image pickup device and more particularly to a solid-state image pickup device including amplification-type light receiving cells.
2. Related Background Art
FIGS. 1 to 4 show a structural example of a conventional solid-state image pickup device, respectively. FIG. 1 is a diagram showing the entire circuit configuration. The pixels 12-11 to 12-mn are arranged in a matrix form in a substrate. Each pixel is formed of an n-channel, normally-on-type (depletion-type) static induction transistor (SIT) 22, a gate capacitor 24 arranged to the floating gate 23 of the SIT 22, and a p-channel, enhancement-type control transistor 25 having a source-drain path connected to the floating gate 23 (in figure, each pixel is shown in broken line). A video voltage Vd is applied to the drain electrode (substrate) of the SIT forming each pixel to connect the row lines 26-1 to 26-m to the gate capacitors of the SITs in each of the row groups of the pixels 21-11 to 21-1n, . . . , 21-ml to 21-mn arranged in the X-direction, so that the vertical scanning circuit (vertical shift register) 27 supplies the row selection signal .phi..sub.G1 to .phi..sub.GM. Each of the column lines 28-1 to 28-n is connected to the sources of the SITs in the column groups of pixels 21-11 to 21-ml, . . . , 21-1n to 21-mn arranged in the Y-direction. The column lines are grounded via the column selection transistors 29-1 to 29-n, the common video line 30, and the load resistor 31. The horizontal scanning circuit (horizontal shift register) 32 applies the column selection signals .phi..sub.S1 to .phi..sub.SN to the gates of the column selection transistors 29-1 to 29-n. Moreover, the control gate line 33 is connected to the gate electrode of the control transistor forming each pixel to apply the control gate signal .phi..sub.C. The overflow drain line 34 is connected to the drain electrode of the control transistor 25 to apply the control drain voltage V.sub.C,
FIG. 2 is a plan view showing the layout of four pixels adjoining to one another. FIG. 3 is a cross-sectional view showing the layout taken along the line A-A'. In this layout example, in order to improve the area efficiency of pixels formed on the substrate 40, the adjoining four pixels are symmetrically formed laterally and horizontally in the figure. The substrate 40 serves as the drain of a static induction transistor and is formed of an n.sup.+ or n-type semiconductor. An n.sup.- epitaxial layer 41 is grown on the substrate 40. An isolation region 42 such as a buried insulating material is formed in the epitaxial layer 41 to separate electrically and optically the adjoining pixels. In each pixel, the gate and the source of the SIT are respectively formed by the p.sup.+ diffusion layer 43 and the n.sup.+ diffusion layer 44 formed on the surface of the epitaxial layer 41. The n.sup.+ diffusion layer 44 is connected to the corresponding column lines 28-i and 28-(i+1) via the wiring layer 45, for example, formed of polycrystalline silicon. The row line electrodes 46-i and 46-(i+1) of, for example, polycrystalline silicon are formed on the p.sup.+ diffusion layer 43 to form the row lines 26-i and 26-(i+1) via the gate oxide film. Thus, a gate capacitor is formed at a portion where the row line electrode confronts the p.sup.+ diffusion layer 43.
The p.sup.+ diffusion region 43 of each pixel is formed so as to extend toward the middle portion of the adjoining four pixels and acts as the source of the control transistor 25 of each pixel. The p.sup.+ diffusion layer 47, which acts as the common drain of the control transistors of the four pixels, is formed in common in the surface of the epitaxial layer 41 in the middle portion among the four pixels, isolated from locating apart from the gate of the SIT from the p.sup.+ diffusion layer forming the source of the control transistor in each pixel. The overflow drain line 34 is connected to the p.sup.+ diffusion layer 47 by way of the wiring electrode 48. The control gate electrode 49 of the control transistor for the four pixels is arranged in common on the gate oxide film over the surface of the epitaxial layer 41 between the p.sup.+ diffusion layers 43 and 47 to form the control gate line 33.
Let us explain below the operation of the above-configuration, with reference to the signal waveforms shown in FIG. 4. In this configuration, as described above, pixel signals are sequentially read out in accordance with the X-Y address system where the row lines 26-1 to 26-m are sequentially selected while the column lines 28-1 to 28-n are sequentially selected. All pixels in a selected row line are simultaneously reset during the horizontal blanking period t.sub.BL, or the duration from the completion of the signal reading period t.sub.H of each row line to the next row selection. In particular, the operation of the pixel 21-22 shall be explained below, with reference to the change in the potential V.sub.G (2,2) of the floating gate shown in FIG. 4. In the floating gate potential V.sub.G (2,2) of the pixel 21-22 shown in FIG. 4, the broken line represents the voltage where there is no incident light during imaging.
At the timing t.sub.1, when the voltage of the row selection signal .phi..sub.G2 applied to the row line 26-2 becomes V.phi..sub.G, the potential of the floating gate of each SIT connected to the row line is nearly boosted by V.phi..sub.G, more exactly, by the value expressed by the following formula: EQU (C.sub.G /C.sub.J +C.sub.G).multidot.V.phi..sub.G
where C.sub.G is the capacitance of the gate capacitor 24 and C.sub.J is the parasitic capacitance of the P.sup.+ diffusion 43. At the timing t.sub.2, when the column line 28-2 or the pixel 21-22 is selected in response to the row selection signal .phi..sub.S2 reaching a high voltage level, the signal current depending on the gate potential V.sub.G (2,2) of the pixel 21-22 flows through the load resistor 31 via the column line 28-2, the column selection transistor 29-2, and the video line 30. The voltage drop across the load resistor 31 is read out as an output signal Vout. This signal reading operation is a nondestructive because the light electric charges accumulated in the floating gate are normally left unchanged.
Next, at the timing t.sub.3 at which the signal reading from all the pixels 21-21 to 21-2n connected to the row line 26-2 has been completed by completing the selection of the final line 28, or at the beginning of the horizontal blanking period t.sub.BL, the control gate signal .phi..sub.C (voltage) applied to the control gate line 33 is -V.phi..sub.C that turns on the control transistor 25. At this time, since the surface potential .phi..sub.S underneath the control gate 49 changes from .phi..sub.S (O) to .phi..sub.S (-V.phi..sub.C), the gate potential V.sub.G (2,2) is forcibly clamped to the potential .phi..sub.S (-V.phi..sub.C). This operation resets the gate potential so that the photo-electric charges Q.sub.P which are accumulated in the gate due to the light illumination are swept out. The voltage -V.phi..sub.C of the control gate signal .phi..sub.S is set in such a manner that the surface potential .phi..sub.S (-V.phi..sub.C) underneath the control gate electrode 49 equals substantially to the pinch-off voltage V.sub.GO of the SIT when the control gate signal is applied while the control drain voltage V.sub.C satisfies .phi..sub.S (-V.phi..sub.C)&gt;V.sub.C.
At the timing t.sub.4, or the final point of the horizontal blanking period t.sub.BL, the row selection signal .phi..sub.G2 is at a low level while the control gate signal .phi..sub.C is at zero volt. Thus, the gate potential V.sub.G (2,2) is lowered in accordance with the formula: V.sub.G (2,2)=.phi..sub.S (-V.phi..sub.C)-V.phi..sub.G . Thereafter, the gate potential is increased by, e.g. Q.sub.P /C.sub.G (=.DELTA.V.sub.GP) because the light electric charges are integrated in accordance with the light received during the imaging period extending to the next reading operation.
In the present configuration, the control gate signal .phi..sub.C is applied to the control gate electrodes of all the pixels in selection state, in addition to the control gate electrode of the pixel connected to a selected row line. Therefore, when the control gate signal .phi..sub.C becomes a voltage -V.sub.C, the surface potential underneath the control gate electrode of a non-selection pixel becomes .phi..sub.S (-V.phi..sub.C), or equals nearly to the pinch-off voltage V.sub.GO of the SIT so that a part of the non-selection pixels accumulate the same amount of light electric charges. Hence, even if the boosted gate potential .DELTA.V.sub.GP satisfies .phi..sub.S (-V.phi..sub.C)-V.phi..sub.G +.DELTA.V.sub.GP &gt;.phi..sub.S (-V.phi..sub.C), or .DELTA.V.sub.GP &gt;V.phi..sub.G, the light electric charges corresponding to the potential .phi..sub.S (-V.phi..sub.C), or the Gate potential exceeding the pinch-off voltage V.sub.GO of the SIT, are swept out to the overflow drain line 34 via the channel underneath the control Gate electrode. Moreover, since the overflow operation of the excessive electric charges is performed to all the non-selection pixels every time the row line is switched, intense incident light does not cause the potential of the floating gate to exceed the pinch-off voltage V.sub.GO. Hence, a half-selection signal phenomenon can be effectively prevented. It can be said that a blooming control is performed equivalently. Since resetting each pixel is performed by clamping the floating gate of the SIT to the potential .phi..sub.S (-V.phi..sub.C) using the control gate signal .phi..sub.C, the residual photo-electric charge can be completely eliminated at the reset time. Hence, the present configuration can completely suppress many afterimage phenomena seen often when resetting is done by biasing forwardly the pn junction between the gate and the source region of the SIT. However, the above-conventional example has an operational limitation that since reading and resetting operations are sequentially performed to each row, the accumulation timing for each row is shifted so that the accumulation time for each row may be varied when a video signal during, for example, a specific period is taken out. The SIT-type and amplification-type image element itself can perform a nondestructive reading operation. However, there has been a problem that with the light receiving surface kept illuminated with light, when the second reading is done without resetting after the first reading, light incident entering between the first and second reading operations varies the signal amount.